The present invention relates to a solid state imaging device provided with an imaging element, such as a CMOS image sensor.
An XY address-type solid state imaging device includes a plurality of imaging elements arranged in a matrix. An image of an object is acquired by scanning the imaging elements in a vertical direction. During this imaging operation, that is, during the operation of an electronic shutter, the electrical charge stored in each imaging element is reset in response to a reset signal. After the reset, the charge stored by each imaging element is read according to a read signal. During the electronic shutter operation, when the input timing of the reset signal and read signal are not appropriate, a band-like electronic shutter noise (difference in brightness level or difference in contrast level) is generated. The shutter noise extends along a horizontal direction in the image. In order to stably obtain high quality images, the generation of such electronic shutter noise must be suppressed.
FIG. 1 shows the pixel array of an XY address-type solid state imaging device. Pixel regions 1 are arranged in a matrix. Each pixel region 1 is connected to a vertical selection line CL and a horizontal selection line SLCT. A photoelectric conversion element, such as a photodiode 2, is formed in each pixel region 1.
In each pixel region 1, an n-channel MOS transistor Tr1 is connected to a power supply VDD, which supplies reset voltage. The cathode of a photodiode 2 is connected to the n-channel MOS transistor Tr1. Accordingly, the reset voltage is supplied through the n-channel MOS transistor Tr1 to the cathode of the photodiode 2. Furthermore, a low potential power supply VSS is connected to the anode of the photodiode 2. A reset signal line RST is connected to the gate of the transistor Tr1.
The source of the transistor Tr1 is connected to the gate of an n-channel MOS transistor Tr2. The drain of the transistor Tr2 is connected to the power supply VDD. The source of the transistor Tr2 is connected to the vertical selection line CL via an n-channel MOS transistor Tr3. The gate of the transistor Tr3 is connected to the horizontal selection line SLCT.
During the imaging operation, the reset signal lines RST are sequentially selected by a reset control circuit. The transistor Tr1 of the pixel region 1 connected to the selected reset signal line RST is turned ON, a photodiode 2 is reset by the reset voltage level of the power supply VDD, and exposure of the photodiode 2 is started. The photodiode 2 is discharged in accordance with the amount of exposure.
Subsequently, the horizontal selection lines SLCT are sequentially selected in accordance with the operation of a vertical scan shift register. The transistor Tr3 connected to the selected horizontal selection line SLCT is turned ON. The pixel data corresponding to the charge potential at the photodiode 2 is output to the associated vertical selection line CL.
A column parallel reading circuit simultaneously reads pixel data, which is read from each pixel region 1 in one horizontal row of the pixel array, through all the vertical selection lines CL. Then, the pixel data is sequentially selected by the horizontal scan shift register and output from an output circuit.
When an imaging device is operated in a so-called rolling shutter mode, the selection of the reset signal lines RST, that is, the selection of the reset row, and the selection of the horizontal selection line SLCT, that is, the selection of the read row, are performed simultaneously. FIG. 2 shows the pixel array at a specific timing. At this time, row L1 is undergoing a reset process, and row L2 is undergoing a read process. The reset row L1 and the read row L2 are separated from each other by a predetermined row spacing L. At the next timing, the reset row L1 and the read row L2 are shifted downward by one row. The row spacing L corresponds to the time from when the reset operation is performed to when the read operation is performed, that is, the integration time (exposure time) of each photodiode 2.
FIG. 3 shows the timing of a rolling shutter operation when the interval between a reset operation AC1 and a read operation AC2 is equivalent to the time for scanning 100 rows (that is, the row spacing L is 100 rows). The total number of rows of the pixel regions 1 is 640, and the vertical blanking period is equivalent to the time for scanning 45 rows.
When the imaging operation of the initial frame FL1 begins, the reset operation AC1 starts to sequentially select the reset signal lines RST. After period t1, which is equivalent to the time for resetting 100 rows, the read operation AC2 is started to sequentially select the horizontal selection lines SLCT. After period t2, the reset operation AC1 of frame FL1 ends. After period t3, the read operation AC2 of frame FL1 ends. Then, when the vertical blanking period t4 which is equivalent to the time for scanning 45 rows elapses, the imaging operation of the first frame FL1 ends, and the reset operation AC1 of the next frame starts.
When each frame is processed, only the reset operation ACL is performed at period t1. At period t2, the reset operation AC1 and the read operation AC2 are performed in parallel (simultaneously). At period t3, only the read operation AC2 is performed. At period t2 during which the two operations of reset and read are performed simultaneously, the load on the power supply VDD is high compared to periods t1 and t3 during which only one of the reset or read operation is performed. Therefore, at period t2, the level of the power supply VDD may be reduced. Fluctuation of the level of the power supply VDD would affect the reset operation AC1 or the read operation AC2 and generate a horizontal band-like electronic shutter noise generated on the imaging screen.
To solve this problem, an imaging device has been proposed to level the load on the power supply VDD by providing a plurality of dummy rows in the pixel array. For example, as shown in FIG. 3, a reset operation is performed on the dummy rows at periods t3 and t4 during which the reset operation AC1 is not performed. A read operation is performed for the dummy rows at periods t1 and t4 during which the read operation is not performed.
In this way, one row always undergoes the reset operation and the read operation. This levels the load on the power supply VDD, suppresses fluctuation of the power supply VDD, and prevents the generation of an electronic shutter noise.
Japanese Laid-Open Patent Publication No. 2001-8109 and Japanese Laid-Open Patent Publication No. 2000-125203 each describe an imaging device in which a reset operation is performed on dummy rows from when a reset operation ends to when a read operation ends.